1. Field of the Invention
The present invention relates to a data line driving circuit for a liquid crystal display device and a method for controlling the same.
2. Description of Related Art
Generally, in a matrix type liquid crystal display, pixels are arranged in a matrix form at intersections of scanning lines and data lines in a row direction and a column direction, respectively, and active elements composed of TFTs (thin film transistors) etc. are respectively arranged at each pixel. Gate electrodes of the above-described active elements are connected to the scanning lines, while the data lines are connected to drain electrodes thereof. In addition, one sides of liquid crystal capacitances equivalent to capacitive loads are connected to source electrodes of the active elements, while the other sides of these liquid crystal capacitances are connected to a common electrode line. A scanning line driving circuit and a data line driving circuit are connected to the above-described scanning lines and data lines, respectively.
In the liquid crystal display, a voltage is applied to the liquid crystal capacitances from the data line driving circuit through the active elements respectively arranged at each pixel by scanning the scanning lines in a top-to-bottom order with the scanning line driving circuit. In the liquid crystal display, an alignment of liquid crystal molecules changes according to the voltage applied to the liquid crystal capacitances, and thereby a light transmittance changes.
In a well-known liquid crystal display device, polarity of a voltage applied to liquid crystal capacitances through TFTs from data lines (hereinafter, referred to as a pixel voltage) is inverted for every predetermined period. Namely, pixels are driven on alternating current (AC).
Here, polarity means positive/negative of a pixel voltage based on a voltage at a common electrode line of liquid crystals (Vcom). Namely, a potential higher than the voltage at the common electrode line Vcom is defined as positive, and a potential lower than that negative.
When a fixed voltage is continued to be applied to the liquid crystal capacitances, in the liquid crystals between electrodes of the liquid crystal capacitances, polarization etc. are generated and a physical property thereof is degraded. Hence, the above-described polarity inversion is required to prevent the above-described degradation by driving pixels on AC. Among polarity inversion systems, for example, as for driving the pixels, there have been known a dot inversion driving system that inverts a polarity of a pixel voltage whenever one scanning line is scanned, a two-line dot inversion driving system that inverts the polarity of the pixel voltage whenever two scanning lines are scanned, a column inversion driving system that inverts a polarity of the scanning line for every frame, etc.
In the inversion driving systems, as described above, the voltages applied to the pixel voltages centering on Vcom are driven on AC. Hence, a voltage range to drive becomes larger. These voltages are supplied from the data line driving circuit, and this data line driving circuit consumes a large power for driving a liquid crystal display. Further, along with larger liquid crystal panels and with increased output of the data line driving circuits, increase of power consumption in the data line driving circuit has become remarkable.
As a prior art that reduces this power consumption in the data line driving circuit, Japanese Unexamined Patent Application Publication No. 9-504389 is disclosed. There is shown in FIG. 4 a data line driving circuit 1 disclosed in Japanese Unexamined Patent Application Publication No. 9-504389. As shown in FIG. 4, the data line driving circuit 1 is composed of data columns 11 to 13, output amplifiers 21 to 23, multiplexers 31 to 33, and an external storage capacitor 40. The multiplexers 31 to 33 are connected to liquid crystal capacitances 51 to 53, respectively.
At the time of the polarity inversion in the liquid crystal display, the multiplexers 31 to 33 are separated the output amplifiers 21 to 23 from the liquid crystal capacitances 51 to 53, and the external storage capacitor 40 and the liquid crystal capacitances 51 to 53 are connected to each other. As a result of this, all the data lines connected to the data line driving circuit 1, i.e., the liquid crystal capacitances 51 to 53 are short circuited to a common node 41. The external storage capacitor 40 is connected to the common node 41, and potentials at the respective data lines are averaged to an intermediate level through this external storage capacitor 40. The data line driving circuit 1 drives each data line from this averaged potential to a desired voltage, thereby alleviating burden of the data line driving circuit and reducing the power consumption.